Digilent 410-279P-KIT Instrukcja Użytkownika Pobierz pdf

1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

ZYBO Reference Manual

Revised February 14, 2014

This manual applies to the ZYBO rev. B

DOC#: 502-279

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 26

Overview

The ZYBO (ZYnq BOard) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit

development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is

based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core

ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. When coupled with the

rich set of multimedia and connectivity peripherals available on the ZYBO, the Zynq Z-7010 can host a whole

system design. The on-board memories, video and audio I/O, dual-role USB, Ethernet, and SD slot will have your

design up-and-ready with no additional hardware needed. Additionally, six Pmod connectors are available to put

any design on an easy growth path.

The Zynq 7010 AP SoC offers the following features:

 650Mhz dual-core Cortex-A9 processor

 DDR3 memory controller with 8 DMA channels

 High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO

 Low-bandwidth peripheral controller: SPI, UART, CAN, I

 Reprogrammable logic equivalent to Artix-7 FPGA

o 4,400 logic slices, each with four 6-input LUTs and 8 flip-flops

o 240 KB of fast block RAM

o Two clock management tiles, each with a phase-locked loop (PLL) and mixed-mode clock

manager (MMCM)

o 80 DSP slices

o Internal clock speeds exceeding 450MHz

o On-chip analog-to-digital converter (XADC)

1 2 3 4 5 6 ... 25 26

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Strona 1 - Overview

1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com ZYBO Reference Manual Revised February 14, 2014 This manual applies to the ZYBO

Strona 2

Strona 3

Strona 4 - 1 Power Supplies

Strona 5 - 2 Zynq AP SoC Architecture

Strona 6

Strona 7

Strona 8 - Table 3. MIO Pinout

Strona 9 - 3 Zynq Configuration

Strona 10 - 3.2 QSPI Boot Mode

Strona 11 - 5 DDR Memory

Strona 12

Strona 13 - 7 MicroSD Slot

Strona 14 - 8 USB OTG

Strona 15 - Oscillator

Strona 16 - 10 HDMI Source/Sink Port

Strona 17 - 11 VGA Port

Strona 18 - 11.1 VGA System Timing

Strona 19 - Display Surface

Strona 20

Strona 21 - Figure 13. ZYBO clocking

Strona 22 - Figure 14. ZYBO GPIO

Strona 23 - S timing diagram

Strona 24 - 16 Pmod Connectors

Strona 25 - 16.2 MIO Pmod

Strona 26 - 16.4 High-Speed Pmod

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