Digilent XUPV2P Instrukcja Użytkownika Strona 1

May 2005EDK Base System Builder (BSB) support for XUPV2P BoardXilinx University Program

May 2005XUPV2P BSB support 10BSB System Overview• Finally BSB lists the system configuration summary for the generated design

May 2005XUPV2P BSB support 11EDK Xilinx Platform Studio (XPS)• After BSB finishes, XPS provides several options for the next path ! Select Download

May 2005XUPV2P BSB support 12Design Implementation• A bunch of things happen under the hood!!– An HDL representation of the design will be created i

May 2005XUPV2P BSB support 13Serial Output• Connect a RS232 serial cable from the XUP-V2P board serial port to the PC • Open a terminal (i.e., Hyper

May 2005XUPV2P BSB support 14You’ve Done It!You have just implemented a System-on-Chip Design using a Xilinx FPGA!

May 2005XUPV2P BSB support 15TestApplication• BSB also generates a simple test application– Each IO EDK peripheral is wiggled by software– LEDs are

May 2005XUPV2P BSB support 16Interfacing with Peripherals1) Disable “Mark to Initialize BRAMs”1) Enable “Mark to Initialize BRAMs”

May 2005XUPV2P BSB support 17TestApplication ModificationUncomment to print valuesUncomment to print values

May 2005XUPV2P BSB support 18Downloading the TestApp• Select Tools!Download and the software is recompiled, programmed into the FPGA bitstream, and

May 2005XUPV2P BSB support 19Simulation Setup• Select Options!Project Options and either point to already compiled libraries or compile them new– No

May 2005XUPV2P BSB support 2What is BSB?• The Base System Builder (BSB) wizard is a software tool that help users quickly build a working system tar

May 2005XUPV2P BSB support 20Simulation Script• Select Tools!Start HDL Simulator – Enter the following commands (or as a do script) at the modelsim

May 2005XUPV2P BSB support 21Modelsim Simulation Commands# Make sure to set EDK to compile for verilogdo system.dovsim system system_conf glbladd wa

May 2005XUPV2P BSB support 22Waveform Output“Ente” being sent to the JTAG UART (part of the actual data transmission)

May 2005XUPV2P BSB support 23Design Size and Implementation Time• Design Size: Currently only 3% of 2VP30 FPGA for entire Microblaze design– There

May 2005XUPV2P BSB support 3Objective• Use a BSB design (or derivative) as the basis for:– Standalone processor based designs– Board Support Package

May 2005XUPV2P BSB support 4XUPV2P Development System

May 2005XUPV2P BSB support 5Mini-Howto• Use EDK 7.1 SP1 (H.11.3) and ISE 7.1 SP2 (H.40)• Launch EDK Platform Studio (XPS) and select BSB flow– Poin

May 2005XUPV2P BSB support 6BSB Board Selection• Select “I would like to create a new design” versus using a previous BSB session as a starting poin

May 2005XUPV2P BSB support 7BSB Processor Selection• BSB supports both the PowerPC405 and Microblaze processors, select the Microblaze processor for

May 2005XUPV2P BSB support 8BSB Processor Options• Accept the default Microblaze Processor Options

May 2005XUPV2P BSB support 9BSB Peripheral Selection• The user can now include various peripherals provided on the board and select among parameters